Phase Lock Loops

XM-A7C9-0409D

PLL, HMC440QS16GE [PCB: 825]
F=10M-2.8G
Integer-N
Recommended Bias Controller: XM-A7D1-0409D

$276

Low Freq (MHz)

10

High Freq (MHz)

2800

Power-up 1. Apply -5V and +15V as marked to power the THS4031IDGNR operational amplifier 2. Apply +5V to VCC to power the HMC440 PLL 3. Apply RF power Power Down 1. Remove RF power 2. Apply 0V to all bias points
A0, A1, A2, A3, A4 are configure as ‘high’ or low’ to set the divide-by behavior of this block. Each digital input defaults to 'High' and is user modifiable to 'low' by applying solder to the encircled ground via. Truth Table ----------------- Output A0 A1 A2 A3 A4 /2 1 0 0 0 0 /3 0 1 0 0 0 /4 1 1 0 0 0 … … … … … … /32 1 1 1 1 1 Note: A0 through A4 are CMOS compatible logic control inputs. A0 is LSB.

Configurations